1. Field of the Invention
The present invention relates to a power supply circuit including a boosting circuit, and more specifically, to a power supply circuit suitable to be built in a driver IC that drives a display unit of a mobile terminal.
2. Description of Related Art
Display devices of mobile data terminals such as a mobile phone and a PDA (Personal Digital Assistants) are configured to operate at a low power supply voltage for reduction of power consumption. On the other hand, the display device adapted to display processed data often needs a voltage higher than those supply voltages. Therefore, generally, a circuit adapted to drive the display device has an internal power supply circuit that generates a necessary drive voltage by boosting the power supply voltage.
An example of such a power supply circuit is shown in Japanese Patent No. 3487581. This power supply circuit 200 is of a charge pump type, and as shown in FIG. 1, the power supply circuit 200 has a charge pump 10 adapted to boost an output voltage of a first power supply 11 (its voltage is designated as VDD) and a smoothing capacitor Co1 adapted to smooth an output voltage VDD2 of this charge pump 10. The charge pump 10 is composed of switches S1 to S4 and a capacitor C1.
Further, the power supply circuit 200 has voltage dividing resistors R1 and R2 that resistance-divide an output voltage VDD2, a comparator 24 such that a connection node of the resistors R1 and R2 (its voltage is designated as COMIN) is connected to its inverting input terminal and a stabilized power supply 23 (its voltage is designated as VREF) is connected to its non-inversion input and that has thereby a hysteresis characteristic.
In addition, the power supply circuit 200 has an AND gate 20 that receives an output of the comparator 24 (its voltage is designated as COMOUT) and a clock signal CLK1 from an oscillator OSC as inputs, a NOT gate 26 that inverts the output of the AND gate 20, and a level shift circuit LS1 that generates a clock signal CLK1A and a clock signal CLK1B obtained by shifting the output of the AND gate 20 and the output of the NOT gate 26, respectively.
Next, a boosting operation of a conventional power supply circuit 200 will be described. Switches S1 and S2 are turned on when the clock signal CLK1B is in an H level, and switches S3 and S4 are turned on when the clock signal CLK1A is in the H level. When the output of the AND gate 20 is in an L level, the charge pump 10 is changed to a state of charge (the switches S1 and S2 are turned on, the switches S3 and S4 are turned off, and the capacitor C1 is changed to the state of charge). When the output of the AND gate 20 is in the H level, the charge pump 10 is changed to a state of discharge (the switches S1 and S2 are turned off, the switches S3 and S4 are turned on, and the capacitor C1 is changed to the state of discharge). Through repetition of charging/discharging operations of this capacitor C1, the output voltage VDD2 of the power supply circuit 200 is raised toward a voltage of two times the power supply voltage VDD.
A target voltage of the output voltage VDD2 is a voltage lower than two times of the power supply voltage VDD, which is set based on ((R1/R2)+1)×VREF. For example, what is necessary to set the target voltage to 5.5 V is just to set R1=R2 if VREF=2.75V. When the output voltage VDD2 reaches the target voltage COMIN>VREF holds and an output voltage COMOUT of the comparator 24 is changed from the H level to the L level. By doing so, an output of the AND gate is changed to the L level at the same time, and the charge pump 10 halts the boosting operation and is changed to the state of charge. This state is a pulse skip state.
When the output voltage VDD2 is lower than the target voltage, COMIN<VREF is met and the output voltage COMOUT of the comparator 24 is changed to the H level from the L level. Since the output voltage COMOUT is in the H level, the clock signal CLK1 becomes an output of the AND gate 20, as it is. Thus, a switching operation of the switches S1 to S4 in response to the clock signals CLK1A and CLK1B that are level shifted are restarted, the charging and discharging operations of the capacitor C1 are repeated, and the output voltage VDD2 is raised toward the target voltage again.
In the above-mentioned operation, a pulse skip operation is an operation in which the charge pump 10 intending to raise the output voltage VDD2 to two times of the power supply voltage VDD is controlled based on the clock signals CLK1A and CLK1B adapted to operate the switches S1 to S4 through negative feedback. After the output voltage VDD2 reaches the target voltage that is lower than the two times of the power supply voltage VDD, the boosting operation of the voltage is stopped and the output voltage VDD2 is adjusted to be in a predetermined range.
FIGS. 2A to 2D are operating waveform diagrams of the conventional power supply circuit 200 in the pulse skip state. As shown by waveforms of the switches S1 to S4 in FIGS. 2B and 2C, on-off periods of the switches S1 to S4 become unfixed in frequency with respect to the clock signal CLK1 because of a decreasing curve of the output voltage VDD2. In other words, since a load current of the output voltage VDD2 is not constant, a gradient of the decreasing curve of the output voltage VDD2 is not constant. Therefore, the on-off periods of the switches S1 to S4 do not become constant. On the other hand, since a current that charges or discharges the capacitor C1 flows through the switches S1 to S4 transiently, the switches S1 to S4 are required to have low impedances. For this reason, in a chip layout, the switches S1 to S4 are very large in size. Thus, peak values of the currents to drive the switches S1 to S4 and peak values of their conduction currents become large. The unfixed frequency operations of these large switches S1 to S4 become noise sources on the chip, and it is likely for them to induce erroneous operations and characteristics degradation in adjacent elements and circuits. For example, when the output voltage VDD2 is stabilized by a regulator and is used by an other circuit, the ripple cannot be fully removed depending on a frequency characteristic of a ripple removal rate of the regulator, since a frequency of a noise or ripple comes out of a design frequency band in which the ripple removal rate is excellent because of the unfixed frequency operation.